cy23s02 spread aware?, frequency multiplier, and zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07155 rev. *e revised august 8, 2011 features spread aware? ? designed to work with ssftg reference signals 90 ps typical jitter out2 200 ps typical jitter out1 65 ps typical output-to-output skew 90 ps typical propagation delay voltage range: 3.3 v 5%, or 5 v 10% output frequency range: 20 mhz - 133 mhz two outputs configuration options allow various multiplication of the reference frequency, refer to table 1 to determine the specific option which meets your multiplication needs available in 8-pin soic package table 1. configuration options fbin fs0 fs1 out1 out2 out1 0 0 2 x ref ref out1 1 0 4 x ref 2 x ref out1 0 1 ref ref/2 out1 1 1 8 x ref 4 x ref out2 0 0 4 x ref 2 x ref out2 1 0 8 x ref 4 x ref out2 0 1 2 x ref ref out2 1 1 16 x ref 8 x ref block diagram pin configuration q fs0 fs1 reference fbin phase detector charge pump loop filter vco 2 output buffer out1 out2 output buffer external feedback connection to out1 or out2, not both input in out2 vdd out1 fs1 8 7 6 5 fbin in gnd fs0 1 2 3 4
cy23s02 document #: 38-07155 rev. *e page 2 of 10 overview the cy23s02 is a two-output zero delay buffer and frequency multiplier. it provides an external feedback path allowing maximum flexibility when implementing the zero delay feature. this is explained further in the sections of this data sheet titled ?how to implement zero delay,? and ?inserting other devices in feedback path.? the cy23s02 is a pin-compat ible upgrade of the cypress w42c70-01. the cy23s02 addresses some application dependent problems experienced by users of the older device. most importantly, it addresses the tracking skew problem induced by a reference that has spread spectrum timing enabled on it. spread aware many systems being designed now utilize a technology called spread spectrum frequency timi ng generation. cypress has been one of the pioneers of ssftg development, and we designed this product so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the ss feature through, the result is a significant amount of tracking skew which may cause problems in systems requ iring synchronization. for more details on spread spectrum timing technology, please see the cypress application note titled, ?emi suppression techniques with spread spectr um frequency timing generator (ssftg) ics.? pin definitions pin name pin no. pin type pin description in 2 i reference input: the output signals will be synchronized to this signal. fbin 1 i feedback input: this input must be fed by one of the outputs (out1 or out2) to ensure proper functionality. if the tr ace between fbin and the output pin being used for feedback is equal in length to the traces between t he outputs and the signal destinations, then the signals received at the destinations will be synchronized to the ref signal input (in). out1 6 o output 1: the frequency of the signal provided by this pin is determined by the feedback signal connected to fbin, and the fs0:1 inputs (see table 1 ). out2 8 o output 2: the frequency of the signal provided by this pin is one-half of the frequency of out1. see table 1 . v dd 7p power connections: connect to 3.3v or 5v. this pin should be bypassed with a 0.1- ? f decoupling capacitor. use ferrite beads to help reduce noise for optimal jitter perfor- mance. gnd 3 p ground connection: connect all grounds to the common system ground plane. fs0:1 4, 5 i function select inputs: tie to vdd (high, 1) or gnd (low, 0) as desired per ta b l e 1 .
cy23s02 document #: 38-07155 rev. *e page 3 of 10 figure 1. schematic/suggested layout how to implement zero delay typically, zero delay buffers (zdbs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. the whole concept behind zdbs is that the signals at the destination chips are all going high at the same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait t hat allows for this compensation. the pll on the zdb causes the feedback signal to be in phase with the reference signal. when laying out the board, match the trace lengths between the output being used for feed back and the fbin input to the pll. if it is desirable to either add a lit tle delay, or slightly precede the input signal, this may also be affected by either making the trace to the fbin pin a little shorter or a little longer than the traces to the devices being clocked. inserting other devices in feedback path another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. this implementation can be applied to any device (asic, multiple output clock buffer /driver, and so on) that is put into the feedback path. referring to figure 2 , if the traces between the asic/buffer and the destination of the clock signal(s) (a) are equal in length to the trace between the buffer and the fbin pin, the signals at the destination(s) device is driven high at the same time the reference clock provided to the zdb goes high. synchronizing the other outputs of the zdb to the outputs from the asic/buffer is more complex however, as any propagation delay in the asic/buffer must be accounted for. figure 2. six output buffer in the feedback path phase alignment in cases where out1 (i.e., the higher frequency output) is connected to fbin input pin t he output out2 rising edges may be either 0 or 180 phase aligned to the in input waveform (as set randomly when the input and/or power is supplied). if out2 is desired to be rising-edge aligned to the in input?s rising edge, then connect the out2 (i.e., the lowest frequency output) to the fbin pin. this setup provides a consistent input-output phase relationship. c8 g ferrite bead power supply connection v+ g c a g fs1 fs0 gnd in fbin 10 f 0.01 f 1 2 3 4 8 7 6 5 reference signal feedback input asic/ buffer zero delay buffer a
cy23s02 document #: 38-07155 rev. *e page 4 of 10 absolute maximum ratings stresses greater than those listed in this table may cause perm anent damage to the device. these represent a stress rating only . operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ?55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : t a = 0 c to 70 c or ?40 c to 85 c, v dd = 3.3 v 5% parameter description test condition min. typ. max. unit i dd supply current unloaded, 133 mhz ? 17 35 ma v il input low voltage ? ? 0.8 v v ih input high voltage 2.0 ? v v ol output low voltage i ol = 8 ma ? ? 0.4 v v oh output high voltage i oh = 8 ma 2.4 ? v i il input low current v in = 0 v ?40 ? 5 ? a i ih input high current v in = v dd ?5 ? a dc electrical characteristics : t a = 0 c to 70 c or ?40 c to 85 c, v dd = 5 v 10% parameter description test condition min. typ. max. unit i dd supply current unloaded, 133 mhz ? 31 50 ma v il input low voltage ? ? 0.8 v v ih input high voltage 2.0 ? v v ol output low voltage i ol = 8 ma ? ? 0.4 v v oh output high voltage i oh = 8 ma 2.4 ? v i il input low current v in = 0 v ?80 ? 5 ? a i ih input high current v in = v dd ??5 ? a
cy23s02 document #: 38-07155 rev. *e page 5 of 10 ac electrical characteristics: t a = 0 c to +70 c or ?40 c to 85 c, v dd = 3.3 v 5% parameter description test condition min. typ. max. unit f in input frequency [1] out2 = ref 10 ? 133 mhz f out output frequency out1 20 ? 133 mhz t r output rise time 0.8 v to 2.0 v, 15-pf load ? ? 3.5 ns t f output fall time 2.0 v to 0.8 v, 15-pf load ? ? 2.5 ns t iclkr input clock rise time [2] ??10ns t iclkf input clock fall time [2] ??10ns t pd fbin to in (reference input) skew [3, 4] ? ? 300 ps t dc duty cycle [5] note 5 40 50 60 % t lock pll lock time power supply stable ? 1.0 ms t jc jitter, cycle-to-cycle [6] out1 ? 200 300 ps out2 ? 90 300 ps t skew output-output skew ? 65 250 ps t pd propagation delay ?350 90 350 ps ac electrical characteristics: t a = 0 c to +70 c or ?40 c to 85 c, v dd = 5 v 10% parameter description test condition min. typ. max. unit f in input frequency [1] out2 = ref 10 ? 133 mhz f out output frequency out1 20 ? 133 mhz t r output rise time 0.8 v to 2.0 v, 15-pf load ? ? 3.5 ns t f output fall time 2.0 v to 0.8 v, 15-pf load ? ? 2.5 ns t iclkr input clock rise time [2] ? ? 10 ns t iclkf input clock fall time [2] ? ? 10 ns t pd fbin to in (reference input) skew [3, 4] ??300ps t d duty cycle [7, 8] 40 50 60 % t lock pll lock time power supply stable ? ? 1.0 ms t jc jitter, cycle-to-cycle [6] out1 ? 200 300 ps out2 ? 90 300 ps t skew output-output skew ? 65 250 ps t pd propagation delay ?350 90 350 ps notes 1. input frequency is limited by output frequency range and input to output frequency multiplication factor (that is determined by circuit configuration). 2. longer input rise and fall time will degrade skew and jitter performance. 3. all ac specifications are measured with a 50 ? transmission line, load terminated with 50 ?? to 1.4 v. 4. skew is measured at 1.4 v on rising edges. 5. duty cycle is measured at 1.4 v. 6. jitter is measured on 133-mhz signal at 1.4 v, low frequency jitter = 350 ps. 7. duty cycle is measured at 1.4 v, 120 mhz. 8. duty cycle at 133 mhz is 35/65 worst case.
cy23s02 document #: 38-07155 rev. *e page 6 of 10 ordering code definitions ordering information ordering code package type temperature grade PB-FREE cy23s02sxi-1 8-pin soic (150 mil) industrial, ?40 c to 85 c cy23s02sxi-1t 8-pin soic (150 mil) - tape and reel industrial, ?40 c to 85 c t = tape and reel x = 1 temperature range: x = c or i c = commercial; i = industrial x = PB-FREE s = soic base device part number company id: cy = cypress 23s02 cy s x - x t x
cy23s02 document #: 38-07155 rev. *e page 7 of 10 package diagram figure 3. 8-pin (150-mil) soic s8 spread aware is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. 51-85066 *e
cy23s02 document #: 38-07155 rev. *e page 8 of 10 acronyms document conventions units of measure acronym description asic application-specific integrated circuit emi electromagnetic interference pll phase-locked loop soic small outline integrated circuit ssftg spread spectrum frequency timing generator vco voltage controlled oscillator zdb zero delay buffer symbol unit of measure ? c degree celsius a microamperes ma milliamperes ms milliseconds mhz megahertz ns nanoseconds pf picofarads ps picoseconds vvolts wwatts
cy23s02 document #: 38-07155 rev. *e page 9 of 10 document history page document title: cy23s02 spread aware?, frequency multiplier, and zero delay buffer document number: 38-07155 rev. ecn no. issue date orig. of change description of change ** 110265 12/18/01 szv change from spec number: 38-00795 to 38-07155 obs 292037 see ecn rgl to obsolete the ds *b 348376 see ecn rgl minor change: re-activate the spec, only commercial are obsoleted, all industrial parts area still active *c 378857 see ecn rgl add typical char data added phase alignment paragraph *d 2894970 03/23/2010 kvm removed inactive part from ordering information table. updated package diagram . *e 3339549 08/08/2011 puru added ordering code definitions . added acronyms and document conventions . updated package diagram .
document #: 38-07155 rev. *e revised august 8, 2011 page 10 of 10 cy23s02 ? cypress semiconductor corporation,2005-2011. the information contained herein is subject to change without notice. cypress se miconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5
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